A microelectronic package commonly contains one or more microelectronic die on which integrated circuits (ICs), microelectromechanical systems (MEMS), or other such devices are fabricated. The bond pads of the microelectronic die may be electrically interconnected to other electrically-conductive features within the microelectronic package, such as metal routing features of a Printed Circuit Board (PCB), an interposer, a leadframe, or a Redistribution Layer (RDL) structure, to list but a few examples. Wire bonding has long been utilized to form such electrical interconnections between the bond pads of the microelectronic die and other electrically-conductive features within a microelectronic package. Wire bonds have traditionally been produced utilizing gold wire; however, the usage of copper wire in wire bonding has recently become more common in view of the lower electrical resistivity and decreased cost of copper as compared to gold and other wire bond materials.
A wire bonded microelectronic die may be repackaged when, for example, failure analysis is desirably performed on the microelectronic die. To repackage a wire bonded microelectronic die, the microelectronic die is initially extracted from its original microelectronic package. The wire bonded microelectronic die may be extracted by first thinning (e.g., grinding) the frontside and/or backside of the microelectronic package. Encapsulant surrounding the microelectronic die, if such encapsulant is present, may then be removed by treatment with an appropriate etchant, such as fuming nitric acid. The newly-extracted microelectronic die is next attached to a second package, which is referred to herein as a “failure analysis package.” Wire bonding may again be employed to electrically interconnect the bond pads of the microelectronic die to electrical contact points, such as contact pads, provided on the failure analysis package. Failure analysis may then be performed on the repackaged microelectronic die to, for example, allow electrical defect localization on the frontside and/or backside of the microelectronic die.
For simplicity and clarity of illustration, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.